1. Technical Field
The present disclosure relates to an information processing device with a plurality of operating modes, and more particularly to information processing devices that can communicate appropriately with external devices.
2. Related Art
Electronic devices such as printers commonly have a power conservation mode to suppress unnecessary power consumption. For example, printers are typically designed to switch the operating mode to an energy saver mode when data requiring printing is not received for a specific period of time. When the printer is in the energy saver mode, the power supply to parts such as the print mechanism and the control unit is stopped appropriately.
While the controller in printers in other electronic devices normally has a single CPU, and the printing process and communication processes, for example, are controlled by the single CPU, devices having two CPUs to accelerate processing and save power have also been proposed.
However, when two CPUs are used, the circuitry becomes more complicated, and arbitration of processing by the two CPUs in each of the operating modes is required.
JP-A-2011-39715 discloses technology for arbitrating memory access from two CPUs.
When an operation request is received in the energy saver mode, the electronic device typically resumes the normal operating mode. Printers, for example, are designed to return to the normal operating mode when a print request is received, but there are various problems with the data reception process in the energy saver mode, including the amount of time required to resume the normal operating mode.
These problems are addressed by the following.
JP-A-2003-122536 describes cancelling the power-saving state of the memory when data is received from a host computer, storing the data in memory by DMA, and then cancelling the power-saving state of the CPU.
JP-A-2002-244834 describes the CPU setting the communication control information used to change from the power-saving mode to the normal transfer mode in the response control unit before entering the power-saving mode, and the response control unit resuming data reception based on the set communication control information when cancelling the power-saving mode without going through the CPU.
In a configuration with two CPUs, however, if one CPU goes into the hibernation state when in the power-saving mode, the other CPU must respond appropriately when a process related to the hibernating CPU occurs. This problem is not addressed by JP-A-2011-39715. It is particularly desirable that processes transmitting data to the external device execute correctly even in the power-saving mode.
JP-A-2003-122536 and JP-A-2002-244834 are silent about how the data reception process is executed in each operating mode in devices having an operating mode that changes the operating speed (clock rate) of the CPU in the printer or other controller (information processing device) in multiple levels.
When the CPU is operating at a low speed (low clock rate) in the power-saving mode, data transfers may not keep pace with data reception in the process whereby the received data is passed through by the CPU. The receive buffer of the reception circuit may therefore become full, and receiving the transmitted data may not be possible. The printer or other controller (information processing device) can therefore preferably adjust the operating mode of the CPU appropriately to the reception process.
An objective of the present invention is therefore to provide an information processing device that has multiple operating modes and can communicate appropriately with external devices in any operating mode. Another objective of the invention is to provide an information processing device that has plural control units and can appropriately execute an arbitration process to transmit data correctly to external devices when one of the control units enters a hibernation state (power-saving mode). Another objective of the invention is to provide an information processing device that can reliably receive data transmitted while the control unit is operating in a low speed mode.